As production geometries of processor systems with their associated memories decrease, the opportunities for defects in the finished products increase. These defects, along with other physical events (e.g., cosmic ray passage), can result in increasing bit error rates in system memories. Along with increasing single bit error rates are the increasing probability of double bit errors in a given area of memory.
To enable quick access to data, processors store recently accessed data in cache memory. To further increase speed of data access, cache memory can be stored in varying levels, each designed to provide data to a next level of cache memory or to the processor.
In cache memory, increasing errors presents additional challenges. In order to take advantage of the speed improvements provided by cache memories, memory cache lines should reliably provide accurate data with minimal memory latency. But double bit and higher error detection mechanisms can take multiple clock cycles and thereby increase memory latency. If such errors are not corrected, then data reloads of a cache line from the system memory or rebooting the system may be in order, which delays processing even further. It is therefore desirable to provide a mechanism for detecting and correcting memory errors while avoiding consumption of clock cycles by data reloads or unnecessary use of higher order error correction techniques, but still making use of single-bit error correction to handle the most common errors.